This invention relates to decoders for digital logic circuits, and more particularly, to digital decoders with true and complementary output lines that operate with short delay times and that can be implemented using relatively few circuit resources.
Digital decoders convert binary input signals on a relatively small number of input lines to a set of corresponding decoded output signals on a relatively larger number of output lines. For example, a two-input digital decoder receives first and second binary signals as inputs and produces four (22) corresponding output signals, whereas a three-input decoder produces eight (23) outputs. Some circuit applications such as memory addressing and tristate driver control require true and complementary control signals. Decoders used in these environments have complementary outputs. For example, a two-input decoder of this type has eight outputs made up of four noninverted and four inverted decoded signals.
Well-designed decoders exhibit short decoding times. Decoders that perform rapidly without undesirable delay times will operate satisfactorily in a variety of integrated circuits and will not unnecessarily slow circuit operation. At the same time, it is important not to use too many circuit resources when implementing a decoder. A decoder that uses a large number of circuit resources will consume a relatively large amount of circuit real estate and may be more prone to failure than less complex designs.
It would therefore be desirable to be able to provide a decoder with an architecture that is capable of supplying both true and complementary decoded outputs while exhibiting short delay times and requiring relatively few circuit resources to implement.